MODULE zs1_7 
"Created by JED2AHDL ABEL 6.00 on Thu Nov 29 23:40:45 19:7 

TITLE 
'STERH(tm) Version 3.42 JEDEC file for: 85c220
'

        zs1_7 device '85c220';

"Pin and Node Declarations
   CLK_7MHZ,  IORQ_,  WR_EN,  RAM_  PIN   1, 2, 3, 4;
   INT,  TRB_IN,  BORDER_,  M1_  PIN   5, 6, 7, 8;
   H0,  H1,  H1M  PIN   9,11,12;
   Pin13,  WR_BUFF,  RAS_,  TRB  PIN  13,14,15,16;
   WE,  CLK_CPU,  WAIT_    PIN  17,18,19;

 H1M,WR_BUFF,WE,CLK_CPU ISTYPE 'Com';
 Pin13,RAS_,TRB,WAIT_ ISTYPE 'Reg_D';
 H1M,Pin13,WR_BUFF,RAS_,TRB,WE,CLK_CPU,WAIT_ ISTYPE 'Buffer';

 X,K,Z,C,P,U,D = .X.,.K.,.Z.,.C.,.P.,.U.,.D.;

EQUATIONS

H1M = (H1  & !TRB.Q 
             # !INT  & !TRB_IN 
             # BORDER_  & H1  & TRB.Q );
H1M.C = CLK_7MHZ;
H1M.OE = ( 1 );

Pin13.D = (!IORQ_  & TRB.Q  & !WAIT_.Q );
Pin13.C = CLK_7MHZ;
Pin13.OE = ( 0 );

WR_BUFF = (H0  & !H1M 
             # !INT  & !TRB_IN );
WR_BUFF.C = CLK_7MHZ;
WR_BUFF.OE = ( 1 );

RAS_.D = (H0 );
RAS_.C = CLK_7MHZ;
RAS_.OE = ( 1 );

TRB.D = (INT  & TRB_IN  & TRB.Q 
             # INT  & !TRB_IN );
TRB.C = CLK_7MHZ;
TRB.OE = ( 1 );

WE = (!RAM_  & !M1_ );
WE.C = CLK_7MHZ;
WE.OE = ( 1 );

CLK_CPU = (CLK_7MHZ  & TRB.Q 
             # !INT  & !TRB_IN 
             # RAS_.Q  & !TRB.Q );
CLK_CPU.C = CLK_7MHZ;
CLK_CPU.OE = ( 1 );

WAIT_.D = (IORQ_  & !WR_EN  & RAM_  & TRB.Q 
             # IORQ_  & M1_  & !H0  & !H1M  & TRB.Q 
             # !TRB.Q  & !WE 
             # !H0  & H1M  & !TRB.Q 
             # IORQ_  & M1_  & !H0  & !H1M  & TRB.Q  & 
               !WAIT_.Q 
             # IORQ_  & !M1_  & H0  & !H1M  & !WAIT_.Q 
             # H0  & !H1M  & !TRB.Q 
             # Pin13.Q );
WAIT_.C = CLK_7MHZ;
WAIT_.OE = ( 1 );


TEST_VECTORS
([]->[])


END